1. Field of the Invention
The invention relates to a method for clock data recovery and an associated device
2. Technical Background and Prior Art
In digital transmission technology, many binary data streams, especially serial data streams with a high bit rate, are transmitted without accompanying clock signal. The goal of clock data recovery (clock data recovery, CDR) is to determine from the received data stream the frequency and phase of the underlying transmission clock pulse.
In a conventional receiver, the recovered transmission clock-pulse signal or clock signal is used for decoding the transmitted bit sequence, wherein the received signal pulse is sampled exactly in the center in order to maximize the signal-noise ratio. In signal analysis, the recovered clock signal is used for the evaluation of the signal quality on the basis of so-called eye diagrams (eye diagram) and other mathematical tools for jitter analysis.
The transmission clock pulse is often determined by means of a PLL (phase-locked loop), a phase-locked control circuit. Various standards prescribe a standardized receiver for signal-quality analysis in the form of PLL properties. The recovered clock signal in this context determines the ideal bit start time according to definition. The evaluation of deviations between the zero passes in the received data stream and in the clock signal forms the basis for the jitter analysis.
The transmission clock pulse is, in principle, recovered in two different ways for the signal analysis or respectively jitter analysis:                The PLL is realized in hardware through the use of components. The user feeds the time-continuous data stream into the PLL and obtains a time-continuous clock signal and the data stream delayed by the processing latency. The data stream and clock signal are synchronised with one another. The method operates online in real time; the data stream is observed constantly.        The PLL is modelled in software with an arithmetic specification. A measuring device takes up a portion of the data stream and applies the clock data recovery algorithm. The clock signal for the recorded data portion is recovered from this. The method generally operates offline, because the processing time of the algorithm is longer than the time duration of the recorded data portion.        
Hardware PLLs known from the prior art can be subdivided into three categories: linear PLLs, digital PLLs and all-digital PLLs (all-digital PLL). All three types of PLL process and generate analog, time-continuous signals, wherein the digital and all-digital PLLs are adapted for the processing of binary, serial data streams.
The term “software PLL” generally denotes the arithmetic specification, which models the functioning of a hardware PLL. One approach is to describe the operation of the analog components mathematically and accordingly to process a highly sampled version of the received data stream. A second approach is based on the observation that only the zero passes in the data stream contain the relevant information for the clock data recovery. In this case, the position of the zero passes is initially determined by interpolation of the stored data portion and from this, the zero passes of the clock signal are then calculated.
FIG. 1 shows the simplified structure of a PLL according to the prior art. The input signal x0(k) is a list with the time position of the zero passes in the data stream, also referred to below as data edges. The calculated clock edges are referred to as y(k). The PLL generates only one clock edge per bit period. If the underlying, time-continuous clock signal is imagined as a sinusoidal oscillation, then y(k) denotes the timing points with phase equal to 0.
The x0(k) are chronologically ordered and processed sequentially. Initially, the time difference e(k) between data edges and clock edges is formed in the phase detector. Since no signal throughput takes place when the transmitter transmits two or more identical bits in succession, the number of data edges is generally smaller than the number of transmitting bits.
The software PLL recovers the underlying clock pulse in the form of a sequence of clock edges y(k). The processing steps are, for example:                Phase or timing error: e(k)=x0(k)−y(k)        Handling of missing edges: a) If |e(k)|<T0/2 set e(k)=0 and reject x0(k);                    b) If |e(k)|>T0/2, set e(k)=0 and retain x0(k) for the next iteration.                        Filtered errors: d(k)=F(q−1)·e(k)        Momentary bit-period estimate: Tb(k)=T0+d(k)        Next clock edge: y(k+1)=q·A(q−1)·Tb(k)        
With a targeted selection of the coefficients of F(q1) and A(q−1), this software PLL can approximate the theoretical PLL transmission function very well provided it operates offline. In the case of a realization operating in real time, it should be borne in mind, that each of the above processing steps requires a certain processing time. The total realization-determined delay falsifies the transmission function of the phase-locked loop and can even endanger stability. As a rule of thumb, a real-time-capable software PLL according to the prior art can only be used for the analysis of data streams, of which the bit period Tb is greater than the processing time for calculating a new clock edge TMIN.